000			01614nam a22003497a 4500
001			5750
003			OSt
005			20240305120606.0
008			240305m20182020-usa|||| |||| 001 0 eng d
020			_a9780367778811 _qpaper back
040			_cCentral library, KU
041			_2eng
082			_2621.381 _a23 _bCAV
100			_aCavanagh, Joseph _e author
245			_aVerilog HDL design examples / _cby Joseph Cavanagh [author.].
250			_a1st ed.
260			_a Boca Raton : _bCRC Press, Taylor & Francis Group, CRC Press is an imprint of the Taylor & Francis Group, an informa business, _c2018
300			_a xvii, 655 p. : _bill. ; _c26 cm.
350			_a4451.00
505	0		_aIntroduction to Logic Design Using Verilog HDL.
505			_aCombinational Logic Design Using Verilog HDL.
505			_aSequential Logic Design Using Verilog HDL.
505			_aComputer Arithmetic Design Using Verilog HDL.
505			_aAppendix A: Event Queue.
505			_a Appendix B: Verilog Project Procedure.
505			_aAppendix C: Answers to Select Problems
520			_aThe book presents the Verilog language with a variety of examples to provide a firm foundation in the design of the digital system using Verilog HDL. It places emphasis on the detailed design of various Verilog projects that include the design module, test bench module, and outputs from the simulator illustrating
650			_aDigital electronics _xComputer-aided design
650			_aLogic design
650			_aVerilog (Computer hardware description language)
942			_2ddc _cBK _n0
999			_c5750 _d5750