MARC details
| 000 -LEADER |
|---|
| fixed length control field |
01614nam a22003497a 4500 |
| 001 - CONTROL NUMBER |
|---|
| KUCL control number |
5750 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| KUCL control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20240305120606.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
240305m20182020-usa|||| |||| 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780367778811 |
| Qualifying information |
paper back |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
Central library, KU |
| 041 ## - LANGUAGE CODE |
|---|
| Source of code |
English |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Edition number |
621.381 |
| Classification number |
23 |
| Item number |
CAV |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Cavanagh, Joseph |
| Relator term |
author |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
Verilog HDL design examples / |
| Statement of responsibility, etc. |
by Joseph Cavanagh [author.]. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
1st ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Boca Raton : |
| Name of publisher, distributor, etc. |
CRC Press, Taylor & Francis Group, CRC Press is an imprint of the Taylor & Francis Group, an informa business, |
| Date of publication, distribution, etc. |
2018 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xvii, 655 p. : |
| Other physical details |
ill. ; |
| Dimensions |
26 cm. |
| 350 ## - PRICE (NR) (BK AM CF MU VM SE) [OBSOLETE] |
|---|
| Price |
4451.00 |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Introduction to Logic Design Using Verilog HDL.<br/> |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Combinational Logic Design Using Verilog HDL. <br/> |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Sequential Logic Design Using Verilog HDL. <br/> |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Computer Arithmetic Design Using Verilog HDL. <br/> |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Appendix A: Event Queue.<br/> |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Appendix B: Verilog Project Procedure. <br/> |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Appendix C: Answers to Select Problems |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
The book presents the Verilog language with a variety of examples to provide a firm foundation in the design of the digital system using Verilog HDL. It places emphasis on the detailed design of various Verilog projects that include the design module, test bench module, and outputs from the simulator illustrating <br/> |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Digital electronics |
| General subdivision |
Computer-aided design |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Logic design |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Verilog (Computer hardware description language) |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |
| Suppress in OPAC |
0 |
